Phase detection circuit and receiver

ABSTRACT

A quadrant deciding section decides the quadrant to which a received signal belongs based on a baseband signal. A rotation projector rotates the received signal and projects the rotated signal to a straight line that intersects orthogonally at the origin with a straight line that bisects the decided quadrant. An integrator integrates the signal after the projection. A one-bit quantizer quantizes the integration result by deciding the sign of the integration result. A delay circuit delays the quantized signal by a predetermined time. An adder adds the decision result and the quantized signal modulo the phase 2π. A low-pass filter sequentially latches phase values after the addition with internal shift registers, converts the phase value to a prescribed specific value when the phase values that cross over 2π exist in the whole data within the registers, and averages the phase values.

TECHNICAL FIELD

The present invention relates to a phase detecting circuit or a receiverthat detects the phase of a frequency-modulated or phase-modulatedreceived signal in the radio communications. The present inventionrelates, more particularly, to a phase detecting circuit or a receiverthat detects the phase of a frequency shift keying (FSK) or phase shitkeying (PSK) signal used in the digital mobile communications.

BACKGROUND ART

A conventional phase detecting circuit is explained below. FIG. 30 showsa structure of the conventional phase detecting circuit disclosed inJapanese Patent Application Laid-open No. 6-77737. The conventionalphase detecting circuit detects a received signal from a base bandsignal. In FIG. 30, a reference numeral 101 denotes a quadrant decidingsection, 102 denotes a rotation projector, 103 denotes an integrator,104 denotes a one-bit quantizer, 105 denotes a delay device, 106 denotesan adder, and 107 denotes a low-pass filter. In the conventionalexample, the rotation projector 102, the integrator 103, the one-bitquantizer 104, the delay device 105, the adder 106, and the quadrantdeciding section 101 constitute a delta sigma modulator.

The operation of the conventional phase detecting circuit is explained.The quadrant deciding section 101 decides the quadrant to which thereceived signal belongs based on a positive or negative sign of thein-phase component and the quadrature component of the received basebandsignal, and outputs a coarse phase value corresponding to the result ofthe decision. When the quadrants of the received signals are in thefirst, the second, the third, and the fourth quadrants, the quadrantdeciding section 101 outputs 0, 1, 2, and 3 respectively.

The rotation projector 102 rotates the reception complex base bandsignal by +π/4 or −π/4 corresponding to the data output from the delaydevice 105. The rotation projector 102 outputs a signed value of therotated signal projected to a straight line that intersects orthogonallyat the origin with a straight line that bisects the quadrant detected bythe rotation projector 101.

The integrator 103 integrates the output from the rotation projector102, and the one-bit quantizer 104 quantizes the integrated value. Theone-bit quantizer 104 outputs 1 when the output from the integrator 103is positive, and outputs 0 when this output is negative. The adder 106adds this output value and the coarse phase value output from thequadrant deciding section 101. The delay device 105 delays the outputfrom the one-bit quantizer 104 by one basic clock (i.e., one cycle) ofthe delta sigma modulator, and outputs the delayed signal to therotation projector 102.

The low-pass filter 107 smoothes the quantization noise based on thephase data added. FIG. 31 shows a structure of the low-pass filter 107.In FIG. 31, a reference numeral 201 denotes shift registers, 202-1,202-2, . . . , and 202-k denote multipliers, and 203 denotes an adder.In the low-pass filter 107, the shift registers 201 sequentially receivethe inputs of phase data output from the adder 106. Each of themultipliers 202-1, . . . , and 202-k multiplies the contents of eachregister with a coefficient, and the adder 203 adds all the multipliedresults. For example, when the coefficient is 1/k, a moving average of Ksequential stages appears as the output from the adder 203.

The operation of the rotation projector 102 is explained. In thefollowing explanation, the reception complex base band signal isexplained as I+jQ. For example, when the output from the delay device105 is 1, the rotation projector 102 rotates the received signal by−π/4, and it is possible to express the received signal as shown by theequation (1).(I+jQ)(cos(π/4)−j sin(π/4))=((I+Q)+j(−I+Q))/√{square root over (2)}  (1)

On the other hand, when the output from the delay device 105 is 0, therotation projector 102 rotates the received signal by +π/4, and it ispossible to express the received signal as shown by the equation (2).(I+jQ)(cos(π/4)+j sin(π/4))=((I−Q)+j(I+Q))/√{square root over (2)}  (2)

Next, the rotation projector 102 projects this signal to a straight linethat intersects orthogonally at the origin with a straight line thatbisects the quadrant detected by the quadrant deciding section 101. Thedirection of the straight line orthogonal with the bisector isdetermined such that the phase increasing direction in the quadrantdetected by the quadrant deciding section 101 coincides with thepositive direction of the straight line.

For example, when the received signal is in the first quadrant, the unitdirection vector of the straight line that intersects orthogonally atthe origin with the straight line that bisects the first quadrantbecomes (−1/√2, 1/√2), when the second quadrant side is determined aspositive. The projection of the rotated received signal to this straightline is expressed as the inner product of the vector with the unitdirection vector of the straight line. Therefore, when the output fromthe delay device 105 is 1, it is possible to express the projection asshown by the equation (3), and when the output from the delay device 105is 0, it is possible to express the projection as shown by the equation(4).((I+Q)/√{square root over (2)},(−I+Q)/√{square root over(2)})·(−1/√{square root over (2)}1/√{square root over (2)})=−I  (3)((I−Q)/√{square root over (2)}, (I+Q)/√{square root over(2)})·(−1/√{square root over (2)}, 1/√{square root over (2)})=Q   (4)

Similarly, when the received signal is in the second quadrant, the unitdirection vector of the straight line that intersects orthogonally withthe straight line that bisects the second quadrant becomes (−1/√2,−1/√2), when the third quadrant side is determined as positive.Therefore, when the output from the delay device 105 is 1, it ispossible to express the projection of the rotated received signal tothis straight line as shown by the equation (5). When the output fromthe delay device 105 is 0, it is possible to express the projection asshown by the equation (6).((I+Q)/√{square root over (2)},(−I+Q)/√{square root over(2)})·(−1/√{square root over (2)},−1/√{square root over (2)})=−Q  (5)((I−Q)/√{square root over (2)}(I+Q)/√{square root over(2)})·(−1/√{square root over (2)},−1/√{square root over (2)})=−I  (6)

Similarly, when the received signal is in the third quadrant, the unitdirection vector of the straight line that intersects orthogonally withthe straight line that bisects the third quadrant becomes (1/√2, −1/√2),when the fourth quadrant side is determined as positive. Therefore, whenthe output from the delay device 105 is 1, it is possible to express theprojection of the rotated received signal to this straight line as shownby the equation (7). When the output from the delay device 105 is 0, itis possible to express the projection as shown by the equation (8).((I+Q)/√{square root over (2)},(−I+Q)/√{square root over(2)})·(1/√{square root over (2)},−1/√{square root over (2)})=I  (7)((I−Q)/√{square root over (2)},(I+Q)/{square root over (2)})·(1/√{squareroot over (2)},−1/√{square root over (2)})=−Q   (8)

Similarly, when the received signal is in the fourth quadrant, the unitdirection vector of the straight line that intersects orthogonally withthe straight line that bisects the fourth quadrant becomes (1/√2, 1/√2),when the first quadrant side is determined as positive. Therefore, whenthe output from the delay device 105 is 1, it is possible to express theprojection of the rotated received signal to this straight line as shownby the equation (9). When the output from the delay device 105 is 0, itis possible to express the projection as shown by the equation (10).((I+Q)/√{square root over (2)},(−I+Q)/√{square root over(2)})·(1/√{square root over (2)},1/√{square root over (2)})=Q   (9)((I−Q)/√{square root over (2)},(I+Q)/√{square root over(2)})·(1/√{square root over (2)},1/√{square root over (2)})=I  (10)

In other words, the rotation projector 102 selectively outputs:

-   (1) −I, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 1,-   (2) Q, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 0,-   (3) −Q, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 1,-   (4) −I, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 0,-   (5) I, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 1,-   (6) −Q, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 0,-   (7) Q, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 1, and-   (8) I, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 0.

The output from the adder 106 is the sum of the coarse phase valueoutput from the quadrant deciding section 101 and the output from theone-bit quantizer 104. Therefore, the output from the adder 106 becomes:

-   (1) 1, when the received signal is in the first quadrant, and also    when the output from the integrator 103 is positive,-   (2) 0, when the received signal is in the first quadrant, and also    when the output from the integrator 103 is negative,-   (3) 2, when the received signal is in the second quadrant, and also    when the output from the integrator 103 is positive,-   (4) 1, when the received signal is in the second quadrant, and also    when the output from the integrator 103 is negative,-   (5) 3, when the received signal is in the third quadrant, and also    when the output from the integrator 103 is positive,-   (6) 2, when the received signal is in the third quadrant, and also    when the output from the integrator 103 is negative,-   (7) 4, when the received signal is in the fourth quadrant, and also    when the output from the integrator 103 is positive, and-   (8) 3, when the received signal is in the fourth quadrant, and also    when the output from the integrator 103 is negative.

In summary, it is possible to express the outputs from the quadrantdeciding section 101, the rotation projector 102, and the one-bitquantizer 104 respectively as shown in FIG. 32.

The method of detecting the phase of the received baseband signal isexplained based on an example that the reception complex base bandsignal A exp(jθ) (=I+jQ) is in the first quadrant. I=A cos θ, and Q=Asin θ.

First, the rotation projector 102 outputs −I or Q to the integrator 103based on the output from the delay device 105. The integrator 103integrates the output from the rotation projector 102. The output fromthe integrator 103 shows the average of the outputs from the rotationprojector 102. The one-bit quantizer 104 decides whether the output fromthe integrator is positive or negative. When the output from theintegrator 103 is positive, the one-bit quantizer 104 outputs 1, and atthe same time, makes the rotation projector 102 output −I via the delaydevice 105. When the output from the integrator 103 is negative, theone-bit quantizer 104 outputs 0, and at the same time, makes therotation projector 102 output Q via the delay device 105. Based on thework of the feedback loop, the output from the integrator 103, that is,the output from the rotation projector 102, is controlled to approach tozero.

The delta sigma modulator (corresponding to the quadrant decidingsection 101, the rotation projector 102, the integrator 103, the one-bitquantizer 104, the delay device 105, and the adder 106) is operated by Ncycles (where N is a natural number). During this period, when theone-bit quantizer 104 outputs positive values by p times and outputsnegative values by q times, “−pI+qQ≈0” and “p+q=N” are established as aresult of the feedback control, when N is sufficiently large. As theadder 106 outputs 1 by p times and outputs 0 by q times, the low-passfilter 107 obtains a simple average of the outputs from the adder 106.It is possible to express the output from the low-pass filter 107 asshown by the equation (11).(1·p+0·q)/N=Q/(I+Q)=tan θ/(1+tan θ)  (11)

Therefore, the output from the low-pass filter 107 becomes

-   (1) tan θ/(1+tan θ)=0, when θ=0,-   (2) tan θ/(1+tan θ)=0.366≈⅓, when θ=π/6,-   (3) tan θ/(1+tan θ)=½, when θ=π/4,-   (4) tan θ/(1+tan θ)=0.634≈⅔, when θ=π/3, and-   (5) tan θ/(1+tan θ)=1, when θ=π/2.

As a result, π/2 times the output from the low-pass filter 107 becomesthe approximate value of the phase. FIG. 33 shows a relationship betweenthe phase of the input signal to the conventional phase detectingcircuit and the detected phase.

FIG. 34 shows waveforms of output signals from the sections of theconventional phase detecting circuit obtained based on a simulationcarried out by the computer. In FIG. 34, the horizontal axis shows time,and the unit of the numbers on the horizontal axis is cycle. In FIG. 34,(a) shows the phase of the received baseband signal; (b) shows thein-phase component and the quadrature component of the received basebandsignal; (c) shows the output from the rotation projector 102; (d) showsthe output from the integrator 103; (e) shows the output from theone-bit quantizer 104; (f) shows the output from the quadrant decidingsection 101; (g) shows the output from the adder 106; and (h) shows theoutput from the low-pass filter 107. As is clear from FIG. 34, theoutput from the low-pass filter 107 shown in (h) is the result ofquantizing the phase of the received baseband signal shown in (a).

The above shows the structure that the reception complex base bandsignal is directly input to the phase detecting circuit. However,instead of this method, it may be arranged as follows. The receivedbaseband signal is rotated by a certain angle. The phase detectingcircuit detects the phase of the signal after the rotation, and obtainsthe phase of the original received baseband signal by subtracting thephase of the rotated angle from this phase. For example, when thecomplex base band signal I+jQ is rotated by 45 degrees, and theresultant signal is multiplied by √2, it is possible to express thissignal as shown by the equation (12).√{square root over (2)}e ^(jπ/4)(I+jQ)=(I−Q)+j(I+Q)  (12)

Therefore, it is possible to obtain the phase of the received basebandsignal in the following order. Signals I−Q, and I+Q are prepared basedon the received baseband signal I and Q. The signals I−Q, and I+Q areinput to the phase detecting circuit. The phase detecting circuitdetects the phases of these signals, and subtracts the quantized valuecorresponding to 45 degrees from the detected phases.

However, according to the conventional phase detecting circuit shown inFIG. 30, when the position of the received signal changes from thefourth quadrant to the first quadrant, for example, the output from theadder 106 of the conventional phase detecting circuit changes from “3 or4” to “0 or 1”. Therefore, the output from the low-pass filter 107becomes the intermediate value of around 2, which is a large deviationfrom around 0 or 4 as a correct phase. As explained above, theconventional phase detecting circuit disregards the cyclicity of thephase, and simply adds the phases. Consequently, there has been aproblem that when the phase of the received signal changes by crossingover 0 or 2π, the phase of the signal output from the low-pass filter107 is not correct (for example, at portion A in (h) in FIG. 34).

The conventional phase detecting circuit has another problem. Let usthink of an example that the position of the received baseband signalI+jQ changes from the first quadrant to the second quadrant. Therotation projector 102 outputs −I (a negative value) or Q (a positivevalue) when the received signal is in the first quadrant. However, whenthe received signal enters the second quadrant, the rotation projector102 outputs −Q (a negative value) or I (a positive value). At a positionnear the boundary between the first quadrant and the second quadrant,the absolute value of I is close to zero, but the absolute value of Q isnot small. Therefore, the output from the rotation projector 102 changesbased on the data output from the delay device 105. When the delaydevice 105 outputs 0, the signal Q in the first quadrant changes to −Iin the second quadrant. When the delay device 105 outputs 1, the signal−I in the first quadrant changes to −Q in the second quadrant. Thus,there is a large change (for example, at portion B in (c) in FIG. 34).As explained above, the conventional phase detecting circuit has aproblem that when the quadrant to which the received signal belongschanges, the output from the rotation projector 102 suddenly changesdiscontinuously, and a temporary error occurs in the phase detectionvalue (for example, at portion C in (h) in FIG. 34).

Further, the analog FM receiver that uses the conventional phasedetecting circuit has a problem that distortion rate characteristic ofthe demodulation signal becomes degraded, as the phase detection valuebecomes inaccurate because of the above two problems. Further, the FSKreceiver and the PSK receiver that use the conventional phase detectingcircuit have a problem that the reception bit error rate characteristicbecomes degraded, for similar reasons.

Therefore, it is an object of the present invention to provide a phasedetecting circuit that can realize accurate phase detection.

DISCLOSURE OF THE INVENTION

According to the present invention, the phase detecting circuitcomprises: a first quantizing unit (corresponding to a phase quantizingsection 401 in the embodiment described later) that quantizes the phaseof a received baseband signal; a converting and selecting unit(corresponding to a converting selector 402) that linearly converts thereceived signal based on a predetermined rule, and selectively outputsthe signal after the linear transformation; an integrating unit(corresponding to the integrator 103) that integrates the output fromthe converting and selecting unit; a second quantizing unit(corresponding to the one-bit quantizer 104) that quantizes theintegration result by deciding the sign of the integration result; adelay unit (corresponding to the delay device 105) that delays theoutput from the second quantizing unit by a predetermined first time,and outputs the delayed signal to the converting and selecting unit; anadding unit (corresponding to the adder 1) that adds the output from thefirst quantizing unit and the output from the second quantizing unitmodulo the quantized value of the phase 2π; and a low-pass filter unit(corresponding to the low-pass filter 2) that sequentially latches phasevalues after the addition with internal shift registers, converts thewhole data within the shift registers based on a predetermined rule whenthe phase values that cross over the quantized value of the phase 2πexist in the whole data, does not carry out the conversion when thephase values that cross over the quantized value of the phase 2π do notexist, averages the phase values in this state, and outputs the phasevalue after smoothing quantization noise.

According to the next invention, the phase detecting circuit comprises:a first quantizing unit that quantizes the phase of a received basebandsignal; a converting and selecting unit (corresponding to a convertingselector 403) that linearly converts the received signal based on apredetermined rule, and selectively outputs the signal after the lineartransformation; an integrating unit that integrates the output from theconverting and selecting unit; a second quantizing unit (correspondingto a one-bit quantizer 5) that quantizes the integration result bydeciding the sign of the integration result based on the output from thefirst quantizing unit; a delay unit that delays the output from thesecond quantizing unit by a predetermined time, and outputs the delayedsignal to the converting and selecting unit; an adding unit that addsthe output from the first quantizing unit and the output from the secondquantizing unit modulo the quantized value of the phase 2π; and alow-pass filter unit that sequentially latches phase values after theaddition with internal shift registers, converts the whole data withinthe shift registers based on a predetermined rule when the phase valuesthat cross over the quantized value of the phase 2π exist in the wholedata, does not carry out the conversion when the phase values that crossover the quantized value of the phase 2π do not exist, averages thephase values in this state, and outputs the phase value after smoothingquantization noise.

According to the next invention, the phase detecting circuit has a deltasigma modulator constituted by the first quantizing unit, the convertingand selecting unit, the integrating unit, the second quantizing unit,the delay unit, and the adding unit.

According to the next invention, the phase detecting circuit comprisesthe delta sigma modulator that has stages of integrators.

According to the present invention, the phase detecting circuit furthercomprises a sample holding circuit unit (corresponding to a sampleholding circuit 3) that holds the received baseband signal at a constantlevel during a predetermined second time, at a pre-stage of the deltasigma modulator.

According to the next invention, the phase detecting circuit comprises:a quadrant deciding unit (corresponding to the quadrant deciding section101) that decides the quadrant to which a received signal belongs basedon a received baseband signal; a rotation projecting unit (correspondingto the rotation projector 102) that rotates the received signal based ona predetermined rule, and projects the rotated signal to a specificstraight line; an integrating unit that integrates the output from therotation projecting unit; a quantizing unit that quantizes theintegration result by deciding the sign of the integration result; adelay unit that delays the quantized signal by a predetermined firsttime, and outputs the delayed signal to the rotation projecting unit; anadding unit that adds the output from the quadrant deciding unit and thequantized signal modulo the phase 2π; and a low-pass filter unit thatsequentially latches phase values after the addition with internal shiftregisters, converts the phase value to a prescribed specific value whenthe phase values that cross over 2π exist in the whole data within theregisters, does not carry out the conversion when the phase values thatcross over 2π do not exist, averages the phase values in this state, andoutputs the phase value after smoothing quantization noise.

According to the next invention, the phase detecting circuit has a deltasigma modulator constituted by the quadrant deciding unit, the rotationprojecting unit, the integrating unit, the quantizing unit, the delayunit, and the adding unit.

According to the next invention, the phase detecting circuit comprises:a quadrant deciding unit that decides the quadrant to which a receivedsignal belongs based on a received baseband signal; a rotationprojecting unit (corresponding to a rotation projector 4) that rotatesthe received signal based on a predetermined rule, and projects therotated signal to a specific straight line; an integrating unit thatintegrates the output from the rotation projecting unit; a quantizingunit (corresponding to the one-bit quantizer 5) that quantizes theintegration result by deciding the sign of the integration result basedon the decided quadrant to which the received signal belongs; a delayunit that delays the quantized signal by a predetermined time, andoutputs the delayed signal to the rotation projecting unit; an addingunit that adds the output from the quadrant deciding unit and thequantized signal modulo the phase 2π; and a low-pass filter unit thatsequentially latches phase values after the addition with internal shiftregisters, converts the phase value to a prescribed specific value whenthe phase values that cross over 2π exist in the whole data within theregisters, does not carry out the conversion when the phase values thatcross over 2π do not exist, averages the phase values in this state, andoutputs the phase value after smoothing quantization noise, wherein thequadrant deciding unit, the rotation projecting unit, the integratingunit, the quantizing unit, the delay unit, and the adding unitconstitute a delta sigma modulator.

According to the next invention, the phase detecting circuit comprisesthe delta sigma modulator that has a plurality of stages of integrators.

According to the next invention, the phase detecting circuit furthercomprises a sample holding circuit unit that holds the received basebandsignal at a constant level during a predetermined second time, at apre-stage of the delta sigma modulator.

According to the next invention, the receiver comprises: a firstquantizing unit that quantizes the phase of a received baseband signal;a converting and selecting unit that linearly converts the receivedbaseband signal based on a predetermined rule, and selectively outputsthe signal after the linear transformation; an integrating unit thatintegrates the output from the converting and selecting unit; a secondquantizing unit that quantizes the integration result by deciding thesign of the integration result; a delay unit that delays the output fromthe second quantizing unit by a predetermined first time, and outputsthe delayed signal to the converting and selecting unit; an adding unitthat adds the output from the first quantizing unit and the output fromthe second quantizing unit modulo the quantized value of the phase 2π; alow-pass filter unit that sequentially latches phase values after theaddition with internal shift registers, converts the whole data withinthe shift registers based on a predetermined rule when the phase valuesthat cross over the quantized value of the phase 2π exist in the wholedata, does not carry out the conversion when the phase values that crossover the quantized value of the phase 2π do not exist, averages thephase values in this state, and outputs the phase value after smoothingquantization noise; and a demodulator (corresponding to the demodulator312) that demodulates the reception data based on the phase value,wherein the first quantizing unit, the converting and selecting unit,the integrating unit, the second quantizing unit, the delay unit, andthe adding unit constitute a delta sigma modulator.

According to the next invention, the receiver comprises: a firstquantizing unit that quantizes the phase of a received baseband signal;a converting and selecting unit that linearly converts the receivedbaseband signal based on a predetermined rule, and selectively outputsthe signal after the linear transformation; an integrating unit thatintegrates the output from the converting and selecting unit; a secondquantizing unit that quantizes the integration result by deciding thesign of the integration result based on the output from the firstquantizing unit; a delay unit that delays the output from the secondquantizing unit by a predetermined time, and outputs the delayed signalto the converting and selecting unit; an adding unit that adds theoutput from the first quantizing unit and the output from the secondquantizing unit modulo the quantized value of the phase 2π; a low-passfilter unit that sequentially latches phase values after the additionwith internal shift registers, converts the whole data within the shiftregisters based on a predetermined rule when the phase values that crossover the quantized value of the phase 2π exist in the whole data, doesnot carry out the conversion when the phase values that cross over thequantized value of the phase 2π do not exist, averages the phase valuesin this state, and outputs the phase value after smoothing quantizationnoise; and a demodulator that demodulates the reception data based onthe phase value, wherein the first quantizing unit, the converting andselecting unit, the integrating unit, the second quantizing unit, thedelay unit, and the adding unit constitute a delta sigma modulator.

According to the next invention, the receiver differentiates the inputsto the first quantizing unit and the converting and selecting unit.

According to the next invention, the receiver comprises: a quadrantdeciding unit that decides the quadrant to which a received signalbelongs; a rotation projecting unit that rotates the received signalbased on a predetermined rule, and projects the rotated signal to aspecific straight line; an integrating unit that integrates the outputfrom the rotation projecting unit; a quantizing unit that quantizes theintegration result by deciding the sign of the integration result; adelay unit that delays the quantized signal by a predetermined firsttime, and outputs the delayed signal to the rotation projecting unit; anadding unit that adds the output from the quadrant deciding unit and thequantized signal modulo the phase 2π; a low-pass filter unit thatsequentially latches phase values after the addition with internal shiftregisters, converts the phase value to a prescribed specific value whenthe phase values that cross over 2π exist in the whole data within theregisters, does not carry out the conversion when the phase values thatcross over 2π do not exist, averages the phase values in this state, andoutputs the phase value after smoothing quantization noise; and ademodulator that demodulates the reception data based on the phasevalue, wherein the quadrant deciding unit, the rotation projecting unit,the integrating unit, the quantizing unit, the delay unit, and theadding unit constitute a delta sigma modulator.

According to the next invention, the receiver comprises: a quadrantdeciding unit that decides the quadrant to which a received signalbelongs; a rotation projecting unit that rotates the received signalbased on a predetermined rule, and projects the rotated signal to aspecific straight line; an integrating unit that integrates the outputfrom the rotation projecting unit; a quantizing unit that quantizes theintegration result by deciding the sign of the integration result basedon the decided quadrant to which the received signal belongs; a delayunit that delays the quantized signal by a predetermined time, andoutputs the delayed signal to the rotation projecting unit; an addingunit that adds the output from the quadrant deciding unit and thequantized signal modulo the phase 2π; a low-pass filter unit thatsequentially latches phase values after the addition with internal shiftregisters, converts the phase value to a prescribed specific values whenthe phase value that cross over 2πexist in the whole data within theregisters, does not carry out the conversion when the phase values thatcross over 2π do not exist, averages the phase values in this state, andoutputs the phase value after smoothing quantization noise; and ademodulator that demodulates the reception data based on the phasevalue, wherein the quadrant deciding unit, the rotation projecting unit,the integrating unit, the quantizing unit, the delay unit, and theadding unit constitute a delta sigma modulator.

According to the next invention, the receiver differentiates the inputsto the quadrant deciding unit and the rotation projecting unit.

According to the next invention, the receiver comprises a delta sigmamodulator of an M order structure.

According to the next invention, in the receiver, the demodulatorcomprises: a timing recovering unit (corresponding to a timingrecovering section 13) that receives a clock that is L times a symbolclock generated by an oscillator, and the phase value, searches thephase value for a data decision timing with the resolution of 1/L of thesymbol clock, and generates a phase detection request timing to operatethe low-pass filter unit; and a data deciding unit (corresponding to adata deciding section 14) that decides the reception data based on thephase value and the data decision timing, wherein the low-pass filterunit operates at the phase detection request timing.

According to the next invention, the receiver further comprises a sampleholding circuit unit that holds the amplified received baseband signalat a constant level during a predetermined second time, at a pre-stageof the delta sigma modulator.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a structure of a phase detecting circuit according to afirst embodiment of the present invention;

FIG. 2 shows a structure of a low-pass filter;

FIG. 3 shows a structure of a phase detecting circuit according to asecond embodiment of the present invention:

FIG. 4 shows a structure of a general phase detecting circuit when thequantization resolution is N;

FIG. 5 explains in detail about the operation of a converting selector;

FIG. 6 shows a structure of a phase detecting circuit according to athird embodiment of the present invention;

FIG. 7 shows a structure of other phase detecting circuit according tothe third embodiment;

FIG. 8 shows a structure of a phase detecting circuit according to afourth embodiment of the present invention;

FIG. 9 shows outputs (the output pattern B) from a quadrant decidingsection, a rotation projector, and a one-bit quantizer;

FIG. 10 shows outputs from the quadrant deciding section, the rotationprojector, and the one-bit quantizer;

FIG. 11 shows outputs from the quadrant deciding section, the rotationprojector, and the one-bit quantizer;

FIG. 12 shows waveforms of output signals from the sections of the phasedetecting circuit according to the fourth embodiment obtained based on asimulation carried out by the computer;

FIG. 13 shows a structure of a phase detecting circuit according to afifth embodiment of the present invention;

FIG. 14 explains in detail about the operation of the phase detectingcircuit according to the fifth embodiment;

FIG. 15 shows a result of the decision about the domain to which thereceived signal belongs;

FIG. 16 shows outputs from the phase quantizing section, the one-bitquantizer, and the converting selector;

FIG. 17 shows outputs from the phase quantizing section, the one-bitquantizer, and the converting selector;

FIG. 18 shows outputs (the output pattern A) from the phase quantizingsection, the one-bit quantizer, and the converting selector;

FIG. 19 shows outputs (the output pattern B) from the phase quantizingsection, the one-bit quantizer, and the converting selector;

FIG. 20 shows a structure of a phase detecting circuit according to asixth embodiment of the present invention;

FIG. 21 shows a structure of a phase detecting circuit according to aseventh embodiment of the present invention;

FIG. 22 shows a structure of other phase detecting circuit according tothe seventh embodiment;

FIG. 23 shows a structure of a receiver comprising the phase detectingcircuit according to an eighth embodiment of the present invention;

FIG. 24 shows a structure of a phase quantizing section (i.e., aquadrant deciding section) in the receiver shown in FIG. 23;

FIG. 25 shows a structure of a converting selector (i.e., a rotationprojector) in the receiver shown in FIG. 23;

FIG. 26 shows a structure of a receiver comprising the phase detectingcircuit according to a ninth embodiment of the present invention;

FIG. 27 shows a structure of a phase quantizing section (i.e., aquadrant deciding section) in the receiver according to the ninthembodiment;

FIG. 28 shows a structure of a converting selector (i.e., a rotationprojector) according to the ninth embodiment;

FIG. 29 shows a structure of a demodulator within the receiver accordingto a tenth embodiment of the present invention;

FIG. 30 shows a structure of the conventional phase detecting circuit;

FIG. 31 shows a structure of the conventional low-pass filter;

FIG. 32 shows outputs (the output pattern A) from the quadrant decidingsection, the rotation projector, and the one-bit quantizer;

FIG. 33 shows a relationship between the phase of the input signal tothe conventional phase detecting circuit and the detected phase; and

FIG. 34 shows waveforms of output signals from the sections of theconventional phase detecting circuit obtained based on a simulationcarried out by the computer;

BEST MODE FOR CARRYING OUT THE INVENTION

Exemplary embodiments of the phase detecting circuit and the receiveraccording to the present invention are explained in detail below withreference to the accompanying drawings. These embodiments do not limitthe present invention.

FIG. 1 shows a structure of a phase detecting circuit according to afirst embodiment of the present invention. In FIG. 1, the referencenumeral 101 denotes the quadrant deciding section, 102 denotes therotation projector, 103 denotes the integrator, 104 denotes the one-bitquantizer, 105 denotes the delay device, a reference numeral 1 denotesan adder, and 2 denotes a low-pass filter. In the present embodiment,the quadrant deciding section 101, the rotation projector 102, theintegrator 103, the one-bit quantizer 104, the delay device 105, and theadder 1 constitute a delta sigma modulator.

The operation of the phase detecting circuit according to the firstembodiment is explained. The sections attached with the same referencenumerals as those in the conventional phase detecting circuit carry outsimilar operations respectively. The quadrant deciding section 101decides the quadrant to which the received signal belongs based on apositive or negative sign of the in-phase component and the quadraturecomponent of the received baseband signal, and outputs a coarse phasevalue corresponding to the result of the decision. When the quadrants ofthe received signals are in the first, the second, the third, and thefourth quadrants, the quadrant deciding section 101 outputs 0, 1, 2, and3 respectively.

The rotation projector 102 rotates the reception complex base bandsignal by +π/4 or −π/4 corresponding to the data output from the delaydevice 105. The rotation projector 102 outputs a signed value of therotated signal projected to a straight line that intersects orthogonallyat the origin with a straight line that bisects the quadrant detected bythe rotation projector 101. The integrator 103 integrates the outputfrom the rotation projector 102, and the one-bit quantizer 104 quantizesthe integrated value. The one-bit quantizer 104 outputs 1 when theoutput from the integrator 103 is positive, and outputs 0 when thisoutput is negative. The delay device 105 delays the output from theone-bit quantizer 104 by one basic clock (i.e., one cycle) of the deltasigma modulator, and outputs the delayed signal to the rotationprojector 102.

The adder 1 adds the coarse phase value output from the quadrantdeciding section 101, and the output from the one-bit quantizer 104modulo the corresponding value of the phase 2π. For example, when thecoarse phase values are expressed as 0, 1, 2, and 3, and also when theoutputs from the one-bit quantizer 104 are 0 and 1, the adder 1 adds thecoarse phase values and the outputs from the one-bit quantizer modulo 4.It is possible to realize this adder easily, by discarding the highestbit of the three-bit adder.

The low-pass filter 2 smoothes the quantization noise based on the phasedata added. FIG. 2 shows a structure of the low-pass filter 2. In FIG.2, the reference numeral 201 denotes the shift registers, 202-1, 202-2,. . . , and 202-k denote the multipliers, a reference numeral 206denotes an adder that executes the addition modulo the correspondingvalue of the phase 2π, 204 denotes a comparing and deciding section, and205-1, 205-2, . . . , and 205-k denote data converters.

In the low-pass filter 2, the shift registers 201 sequentially receivethe inputs of phase data output from the adder 1. When the comparing anddeciding section 204 decides that 0 and 3 exist in the contents of thephase data input to the shift registers, the data converters 205-1 to205-k convert the output data from the shift registers as follows. Thedata converters convert 0 to 4, and convert 1 to 5, by leaving 2 as 2,and leaving 3 as 3. On the other hand, when the comparing and decidingsection 204 decides that 0 and 3 do not exist in the contents of thephase data input to the shift registers, the data converters 205-1 to205-k output straight the output data from the shift registers, withoutexecuting the conversion. The multipliers 202-1 to 202-k multiply theoutput from each data converter by a coefficient ci (i=1 to k). Theadder 206 adds all the multiplied results modulo the phase 2π. The adder206 executes the addition modulo the phase 2π, by outputting theremainder module to 4, after executing the normal addition.

According to the present embodiment, the adder 1 executes the additionmodulo the phase 2π. When the outputs from the shift registers 201 to beexecuted include the phase data that cross over 2π, the low-pass filter2 executes the processing by converting the range 0 to 2π (whichcorrespond to 0 to 3 in the outputs from the shift registers) of thephase data to the range π to 3π (which correspond to 2 to 5 in theoutputs from the data converter), and thereafter returns the range ofthe phase data to 0 to 2π (which correspond to 0 to 3). Based on thisarrangement, it is possible to obtain the accurate result of averagingthe phase data. Therefore, it is possible to realize accurate phasedetection.

In the first embodiment, the quadrant deciding section 101 quantizes thephase of the received signal in two bits. In the second embodiment, thecase where the quantization resolution is N (natural number) isexplained.

FIG. 3 shows a structure of a phase detecting circuit according to asecond embodiment of the present invention. In FIG. 3, a referencenumeral 401 denotes a phase quantizing section, and 402 denotes aconverting selector. In. FIG. 3, the sections having the same structuresas those in the first embodiment are attached with like referencenumerals, and their explanation is omitted. In the present embodiment,the phase quantizing section 401, the converting selector 402, theintegrator 103, the one-bit quantizer 104, the delay device 105, and theadder 1 constitute the delta sigma modulator.

Before explaining the operation of the phase detecting circuit accordingto the second embodiment, the operation of the general phase detectingcircuit when the quantization resolution is N will be explained. FIG. 4shows a structure of the general phase detecting circuit when thequantization resolution is N.

First, the plane of the signal is divided into N sectorial domains basedon the central angle of 2π/N, with the origin as the center. A point ofthe phase equal to or greater than 2(i−1)π/N and less than 2iπ/N belongsto a domain i (where i is a natural number). The phase quantizingsection 401 decides the domain to which the reception complex base bandsignal belongs, and outputs a phase quantized value that corresponds tothe result of the decision. When the received signal belongs to thedomain i, the phase quantizing section 401 outputs i−1.

The converting selector 402 rotates the reception complex base bandsignal by +π/N or −π/N, corresponding to the data output from the delaydevice 105. Further, the converting selector 402 outputs a signed valueof the rotated signal projected to a straight line that intersectsorthogonally at the origin with a straight line that bisects the domainthat includes the received signal detected by the phase quantizingsection 401. The integrator 103 integrates the output from theconverting selector 402, and the one-bit quantizer 104 quantizes theintegrated value. The one-bit quantizer 104 outputs 0 when the outputfrom the integrator 103 is positive, for example. The adder 106 addsthis output value and the phase quantized value output from the phasequantizing section 401. The delay device 105 delays the output from theone-bit quantizer 104 by one basic clock of the delta sigma modulator,and outputs the delayed signal to the converting selector 402.

The operation of the converting selector 402 will now be explained indetail. In the following explanation, it is assumed that the receptioncomplex base band signal A exp(jθ) (=I+jQ) belongs to the domain i. Asshown in FIG. 5, the phase of the reception complex base band signal isexpressed as θ=2 (i−1)π/N+φ. φ is a value equal to or greater than 0 andless than 2 π/N. For example, when the output from the delay device 105is 1, the received signal is rotated by −π/N, and it is possible toexpress this signal as shown by the equation (13). $\begin{matrix}\begin{matrix}{{A\quad\exp\quad j\quad{\theta \cdot {\exp\left( {{- j}\quad\frac{\pi}{N}} \right)}}} = {{A\quad\cos\left( {{j\quad\frac{\left( {{2i} - 3} \right)\pi}{N}} + \phi} \right)} +}} \\{j\quad A\quad{\sin\left( {\frac{\left( {{2i} - 3} \right)\pi}{N} + \phi} \right)}}\end{matrix} & (13)\end{matrix}$

On the other hand, when the output from the delay device 105 is 0, thereceived signal is rotated by +π/N, and it is possible to express thissignal as shown by the equation (14). $\begin{matrix}\begin{matrix}{{A\quad\exp\quad j\quad{\theta \cdot {\exp\left( {j\quad\frac{\pi}{N}} \right)}}} = {{A\quad\cos\left( {{j\quad\frac{\left( {{2i} - 1} \right)\pi}{N}} + \phi} \right)} +}} \\{j\quad A\quad{\sin\left( {\frac{\left( {{2i} - 1} \right)\pi}{N} + \phi} \right)}}\end{matrix} & (14)\end{matrix}$

Next, the converting selector 402 projects this signal to the straightline that intersects orthogonally with the straight line that bisectsthe region detected by the phase quantizing section 401. The directionof the orthogonal straight line is determined such that the phaseincreasing direction in the region detected by the phase quantizingsection 401 coincides with the positive direction of the straight line.As a result, the unit direction vector of the straight line thatintersects orthogonally at the origin with the straight line thatbisects the region i becomes (−sin(2i−1) π/N, cos((2i−1) π/N). Theprojection of the rotated received signal to this straight line isexpressed as the inner product of the vector with the unit directionvector of the straight line. Therefore, when the output from the delaydevice 105 is 1, it is possible to express the projection as shown bythe equation (16), and when the output from the delay device 105 is 0,it is possible to express the projection as shown by the equation (16).$\begin{matrix}{{\left( {{A\quad{\cos\left( {\frac{\left( {{2i} - 3} \right)\pi}{N} + \phi} \right)}},{A\quad{\sin\left( {\frac{\left( {{2i} - 3} \right)\pi}{N} + \phi} \right)}}} \right) \cdot \left( {{{- \sin}\frac{\left( {{2i} - 1} \right)\pi}{N}},{\cos\frac{\left( {{2i} - 1} \right)\pi}{N}}} \right)} = {{- A}\quad{\sin\left( {\frac{2\quad\pi}{N} - \phi} \right)}}} & (15) \\{{\left( {{A\quad{\cos\left( {\frac{\left( {{2i} - 1} \right)\pi}{N} + \phi} \right)}},{A\quad{\sin\left( {\frac{\left( {{2i} - 1} \right)\pi}{N} + \phi} \right)}}} \right) \cdot \left( {{{- \sin}\frac{\left( {{2i} - 1} \right)\pi}{N}},{\cos\frac{\left( {{2i} - 1} \right)\pi}{N}}} \right)} = {A\quad\sin\quad\phi}} & (16)\end{matrix}$

In other words, it is possible to express the output from the convertingselector 402 as shown by the equation (17) or the equation (18). Eachoutput becomes a linear transformation from the reception complex baseband signal. $\begin{matrix}{{{- A}\quad{\sin\left( {\frac{2\quad\pi}{N} - \phi} \right)}} = {{{- I}\quad\sin\quad\frac{2i\quad\pi}{N}} + {Q\quad\cos\quad\frac{2i\quad\pi}{N}}}} & (17) \\{{A\quad\sin\quad\phi} = {{{- I}\quad\sin\quad\frac{2\left( {i - 1} \right)\quad\pi}{N}} + {Q\quad\cos\quad\frac{2\left( {i - 1} \right)\quad\pi}{N}}}} & (18)\end{matrix}$

As a result, the converting selector 402 first outputs −A sin (2π/N −φ)or A sin φ to the integrator 103. The integrator integrates the receivedinput, and outputs an average value of the outputs from the convertingselector 402. The one-bit quantizer 104 decides whether the output fromthe integrator 103 is positive or negative. When the output from theintegrator 103 is positive, the one-bit quantizer outputs 1, and at thesame time, makes the converting selector 402 output −A sin (2π/N−φ) viathe delay device 105. When the output from the integrator 103 isnegative, the one-bit quantizer outputs 0, and at the same time, makesthe converting selector 402 output −A sin φ via the delay device 105.Based on the work of the feedback loop, the output from the integrator103, that is, the output from the converting selector 402, is controlledto approach to zero.

The delta sigma modulator (corresponding to the phase quantizing section401, the converting selector 402, the integrator 103, the one-bitquantizer 104, the delay device 105, and the adder 106) is operated by Mcycles (where M is a natural number). During this period, when theone-bit quantizer 104 outputs positive values by p times and outputsnegative values by q times, “−p sin (2π/N−φ)+q sin φ≈0” and “p+q=M” areestablished as a result of the feedback control, when M is sufficientlylarge.

As the received signal belongs to the region i, the phase quantizingsection 401 outputs i−1, and the one-bit quantizer 104 outputs 1 by ptimes and outputs 0 by q times. Therefore, the adder 106 outputs i by ptimes, and outputs i−1 by q times. The low-pass filter 107 obtains asimple average of the outputs from the adder 106, and it is possible toexpress the output from the low-pass filter 107 as shown by the equation(19). $\begin{matrix}{\frac{{i \cdot p} + {\left( {i - 1} \right)q}}{M} = {i - \frac{\sin\left( {{2\quad{\pi/N}} - \phi} \right)}{{\sin\quad\phi} + {\sin\left( {{2\quad{\pi/N}} - \phi} \right)}}}} & (19)\end{matrix}$

In other words, the output from the low-pass filter 107 becomes asfollows:

-   (1) When φ=0, that is, when θ=2 (i−1) π/N, the right-hand side of    the equation (17) becomes equal to i−1.-   (2) When φ=π/N, that is, when θ=(2i−1) π/N, the right-hand side of    the equation (17) becomes equal to i−½.-   (3) When φ=2π/N, that is, when θ=2i π/N, the right-hand side of the    equation (17) becomes equal to i. As a result, the output of the    low-pass filter 107 times 2π/N becomes an approximate value of the    phase.

The operation of the phase detecting circuit according to the presentembodiment is explained next. Only the operation different from that ofthe above-described general phase detecting circuit is explained. Theadder 1 adds the phase quantized value output from the phase quantizingsection 401 and the output from the one-bit quantizer 104 modulo thequantized value of the phase 2π.

The low-pass filter 2 smoothes the quantization noise based on the addedphase data, in a similar process to the process according to the firstembodiment.

According to the present embodiment, it is possible to obtain theeffects similar to those of the first embodiment, and it is alsopossible to obtain the effects when the quantization resolution is N(natural number).

FIG. 6 and FIG. 7 show structures of a phase detecting circuit accordingto the third embodiment. In FIG. 6 and FIG. 7, a reference numeral 3denotes a sample holding circuit. In FIG. 6 and FIG. 7, the sectionshaving the same structures as those in the first embodiment or thesecond embodiment are attached with like reference numerals, and theirexplanation is omitted. The structure shown in FIG. 6 has the sampleholding circuit 3 added to the structure (FIG. 1) according to the firstembodiment. The structure shown in FIG. 7 has the sample holding circuit3 added to the structure (FIG. 3) according to the second embodiment.However, the structures of the present embodiment are not limited tothese structures. It is also possible to apply the sample holdingcircuit 3 to the structure shown in FIG. 30 or FIG. 4.

The sample holding circuit 3 holds the received baseband signal at aconstant level during the period of N cycles until when a sufficientlyhigh precision quantized value of the phase is obtained based on thedelta sigma conversion by the delta sigma modulator (corresponding tothe quadrant deciding section 101, the rotation projector 102, theintegrator 103, the one-bit quantizer 104, the delay device 105, and theadder 1, in FIG. 6, and also corresponding to the phase quantizingsection 401, the converting selector 402, the integrator 103, theone-bit quantizer 104, the delay device 105, and the adder 1, in FIG. 7)within the phase detecting circuit.

According to the present embodiment, the outputs from the rotationprojector 102 and the converting selector 402 become constant during theoperation of the delta sigma modulator. Therefore, it is possible toobtain a more accurate phase detection value.

According to the third embodiment, the received baseband signal is heldat a constant level during the period of N cycles until when asufficiently high precision quantized value of the phase is obtainedbased on the delta sigma conversion. Therefore, the following problemsremain.

For example, in the FSK or the PSK of the digital modulation system, thetransmission signal takes a value having a constant frequency or aconstant phase at each symbol clock. Actually, the band is limited torestrict the spread of the spectrum of the transmission signal.Therefore, the transmission signal takes a constant frequency or aconstant phase at a specific timing of each symbol clock. The frequencyand the phase change smoothly at other portions. Consequently, thereceiver cannot decide a frequency or a phase at an optional timing. Thereceiver needs to find the timing when the transmission signal takes aconstant frequency or a constant phase, and decide the data insynchronism with this timing. Therefore, the receiver usually detectsthe frequency or the phase of the received signal at intervals of ⅛ or{fraction (1/16)} of the symbol clock, and finds a suitable datadecision timing from among these frequencies or phases.

When the phase detecting circuit according to the third embodimentdetects a phase at the period of ⅛ of the symbol clock, for example, thesample holding circuit 3 holds the base band signal received at eachdetection timing, and the delta sigma modulator is operated by N cycles.Therefore, clocks of eight N times the symbol clock are necessary, whichresults in large power consumption.

The fourth embodiment solves the above problems. FIG. 8 shows astructure of the phase detecting circuit according to a fourthembodiment of the present invention. In FIG. 8, a reference numeral 4denotes a rotation projector that carries out the operation differentfrom that of the rotation projector 102, and 5 denotes a one-bitquantizer that carries out the operation different from that of theone-bit quantizer 104. In FIG. 8, the sections having the samestructures as those in the first to the third embodiments are attachedwith like reference numerals, and their explanation is omitted. In thepresent embodiment, the quadrant deciding section 101, the rotationprojector 4, the integrator 103, the one-bit quantizer 5, the delaydevice 105, and the adder 1 constitute the delta sigma modulator. Thestructure shown in FIG. 8 is a modified structure of the structure(FIG. 1) according to the first embodiment, for convenience ofexplanation. However, the structure according to the present embodimentis not limited to this structure. For example, it is also possible tomodify the conventional structure (FIG. 30) to obtain the structure ofthe present embodiment.

The operation of the phase detecting circuit according to the thirdembodiment is explained next. The sections having the same referencenumerals as those according to the first embodiment carry out similaroperations.

The rotation projector 4 and the one-bit quantizer 5 operate accordingto the output from the quadrant deciding section 101. For example, theone-bit quantizer 5 decides the sign of the output from the integrator103 according to the output from the quadrant deciding section 101, andoutputs:

-   (1) 1, when the received signal is in the first quadrant, and also    when the output from the integrator 103 is positive,-   (2) 0, when the received signal is in the first quadrant, and also    when the output from the integrator 103 is negative,-   (3) 0, when the received signal is in the second quadrant, and also    when the output from the integrator 103 is positive,-   (4) 1, when the received signal is in the second quadrant, and also    when the output from the integrator 103 is negative,-   (5) 1, when the received signal is in the third quadrant, and also    when the output from the integrator 103 is positive,-   (6) 0, when the received signal is in the third quadrant, and also    when the output from the integrator 103 is negative,-   (7) 0, when the received signal is in the fourth quadrant, and also    when the output from the integrator 103 is positive, and-   (8) 1, when the received signal is in the fourth quadrant, and also    when the output from the integrator 103 is negative.

The rotation projector 4 selectively outputs:

-   (1) −I, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 1,-   (2) Q, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 0,-   (3) Q, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 1,-   (4) I, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 0,-   (5) I, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 1,-   (6) −Q, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 0,-   (7) −Q, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 1, and-   (8) −I, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 0.

The one-bit quantizer 5 decides the sign of the output from theintegrator 103 according to the output from the quadrant decidingsection 101, and outputs:

-   (1) 0, when the received signal is in the first quadrant, and also    when the output from the integrator 103 is positive,-   (2) 1, when the received signal is in the first quadrant, and also    when the output from the integrator 103 is negative,-   (3) 1, when the received signal is in the second quadrant, and also    when the output from the integrator 103 is positive,-   (4) 0, when the received signal is in the second quadrant, and also    when the output from the integrator 103 is negative,-   (5) 0, when the received signal is in the third quadrant, and also    when the output from the integrator 103 is positive,-   (6) 1, when the received signal is in the third quadrant, and also    when the output from the integrator 103 is negative,-   (7) 1, when the received signal is in the fourth quadrant, and also    when the output from the integrator 103 is positive, and-   (8) 0, when the received signal is in the fourth quadrant, and also    when the output from the integrator 103 is negative.

The rotation projector 4 selectively outputs:

-   (1) I, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 1,-   (2) −Q, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 0,-   (3) −Q, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 1,-   (4) −I, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 0,-   (5) −I, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 1,-   (6) Q, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 0,-   (7) Q, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 1, and-   (8) I, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 0.

The reason why it is possible to detect each phase based on the aboveoperation is explained. In the phase detecting circuit according to thefirst embodiment, the one-bit quantizer outputs 1 when the output fromthe integrator 103 is positive, and outputs 0 when the output from theintegrator 103 is negative, and the rotation projector 102 selectivelyoutputs:

-   (1) −I, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 1,-   (2) Q, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 0,-   (3) −Q, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 1,-   (4) −I, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 0,-   (5) I, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 1,-   (6) −Q, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 0,-   (7) Q, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 1, and-   (8) I, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 0.

In summary, it is possible to express the outputs from the quadrantdeciding section 101, the rotation projector 4, and the one-bitquantizer 5 respectively as shown in FIG. 32. The pattern of theseoutputs is called the output pattern A, for convenience.

On the other hand, when the positive or negative sign of the signaloutput from the rotation projector 4 is inverted, the sign of the outputfrom the integrator 103 is also inverted. In this case, when the sign ofthe output signal is inverted, the decision made by the one-bitquantizer 5 is set opposite at the same time, so that the one-bitquantizer 5 outputs 0 when the output from the integrator 103 ispositive, and outputs 1 when the output from the integrator 103 isnegative. When the signs are inverted as explained above, the outputsmade from the one-bit quantizer 5 remain unchanged.

In other words, the one-bit quantizer 5 outputs 0 when the output fromthe integrator 103 is positive, and outputs 1 when the output from theintegrator 103 is negative, and the rotation projector 4 selectivelyoutputs:

-   (1) I, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 1,-   (2) −Q, when the received signal is in the first quadrant, and also    when the output from the delay device 105 is 0,-   (3) Q, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 1,-   (4) I, when the received signal is in the second quadrant, and also    when the output from the delay device 105 is 0,-   (5) −I, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 1,-   (6) Q, when the received signal is in the third quadrant, and also    when the output from the delay device 105 is 0,-   (7) −Q, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 1, and-   (8) −I, when the received signal is in the fourth quadrant, and also    when the output from the delay device 105 is 0.

In summary, it is possible to express the outputs from the quadrantdeciding section 101, the rotation projector 4, and the one-bitquantizer 5 respectively as shown in FIG. 9. The pattern of theseoutputs is called the output pattern B, for convenience.

The phase detecting circuit according to the present embodiment outputsthe output patterns A and B in combination for each quadrant. In otherwords, the phase detecting circuit outputs the output pattern A when thereceived signal is in the first quadrant, outputs the output pattern Bwhen the received signal is in the second quadrant, outputs the outputpattern A when the received signal is in the third quadrant, and outputsthe output pattern B when the received signal is in the fourth quadrant(as shown in FIG. 10). Alternatively, the phase detecting circuitoutputs the output pattern B when the received signal is in the firstquadrant, outputs the output pattern A when the received signal is inthe second quadrant, outputs the output pattern B when the receivedsignal is in the third quadrant, and outputs the output pattern A whenthe received signal is in the fourth quadrant (as shown in FIG. 11).

Based on the above arrangement, in FIG. 10, for example, when thereceived baseband signal I+jQ shifts from the first quadrant to thesecond quadrant, the rotation projector 4 outputs −I (a negative value)or Q (a positive value) when the received signal is in the firstquadrant, and outputs I (a negative value) or Q (a positive value) whenthe received signal shifts to the second quadrant. The absolute value ofI is close to zero, at a position near the boundary between the firstquadrant and the second quadrant. Therefore, the change in the outputfrom the rotation projector 4 becomes small.

According to the present embodiment, even when the quadrant to which thereceived signal belongs changes, the change in the output from therotation projector 4 becomes small, as the absolute value of I is closeto zero at a position near the boundary between the quadrants. As aresult, the phase detection value obtained by the delta sigma modulatorbecomes accurate. In the present embodiment, it is also possible to usethe sample holding circuit 3, like in the structure according to thethird embodiment.

FIG. 12 shows waveforms of output signals from the sections of the phasedetecting circuit according to the fourth embodiment obtained based on asimulation carried out by the computer. In FIG. 12, the horizontal axisshows time, and the unit of the numbers on the horizontal axis is cycle.In FIG. 12, (a) shows the phase of the received baseband signal; (b)shows the in-phase component and the quadrature component of thereceived baseband signal; (c) shows the output from the rotationprojector 4; (d) shows the output from the integrator 103; (e) shows theoutput from the one-bit quantizer 5; (f) shows the output from thequadrant deciding section 101; (g) shows the output from the adder 1;and (h) shows the output from the low-pass filter 2. As is clear fromFIG. 12, in the present embodiment, even when the quadrant to which thereceived signal belongs changes, the error in the phase detection valuebecomes smaller than that in the conventional phase detecting circuit.

In the fourth embodiment, the quadrant deciding section 101 quantizesthe phase of the received signal in two bits. In the fifth embodiment,as an exemplification of the case where the quantization resolution is N(natural number), the quantization of the phase of the received signalin three bits is explained.

FIG. 13 shows a structure of a phase detecting circuit according to afifth embodiment of the present invention. A reference numeral 403denotes a converting selector. In FIG. 13, the sections having the samestructures as those in the fourth embodiment are attached with likereference numerals, and their explanation is omitted. FIG. 14 explainsin detail about the operation of the phase detecting circuit accordingto the fifth embodiment.

First, the plane of the signal is divided into eight sectorial domainsbased on the central angle of π/4, with the origin as the center. Apoint of the phase equal to or greater than (i−1)π/4 and less than iπ/4belongs to the domain i (where i is a natural number). The phasequantizing section 401 decides the domain to which the reception complexbase band signal belongs, and outputs a phase quantized value thatcorresponds to the result of the decision. When the received signalbelongs to the domain i, the phase quantizing section 401 outputs i−1.The phase quantizing section 401 decides the quadrant to which thereceived signal belongs based on a positive or negative sign of thein-phase component and the quadrature component of the received basebandsignal and the size of the absolute value, and outputs the phasequantized value corresponding to the result of the decision, as shown inFIG. 15.

The converting selector 403 and the one-bit quantizer 5 operateaccording to the output from the phase quantizing section 401. Theone-bit quantizer 5 decides the sign of the output from the integrator103 according to the output from the phase quantizing section 401. FIG.16 and FIG. 17 show outputs from the phase quantizing section 401, theone-bit quantizer 5, and the converting selector 403.

The reason why it is possible to detect each phase based on the aboveoperation is explained. In the phase detecting circuit according to thesecond embodiment, it is possible to express the outputs from theone-bit quantizer 5 and the converting selector 403 as shown in FIG. 18.The pattern of these outputs is called the output pattern A, forconvenience.

On the other hand, when the positive or negative sign of the signaloutput from the converting selector 403 is inverted, the sign of theoutput from the integrator 103 is also inverted. In this case, when thesign of the output signal is inverted, the decision made by the one-bitquantizer 5 is set opposite at the same time, so that the one-bitquantizer 5 outputs 0 when the output from the integrator 103 ispositive, and outputs 1 when the output from the integrator 103 isnegative. When the signs are inverted as explained above, the outputsmade from the one-bit quantizer 5 remain unchanged. It is possible toexpress the outputs from the one-bit quantizer 5 and the convertingselector 403 as shown in FIG. 19. The pattern of these outputs is calledthe output pattern B, for convenience.

The phase detecting circuit according to the present embodiment outputsthe output patterns A and B in combination for each domain. In otherwords, the phase detecting circuit outputs the output pattern A when thereceived signal is in an odd-order domain, and outputs the outputpattern B when the received signal is in an even-order domain (as shownin FIG. 16). Alternatively, the phase detecting circuit outputs theoutput pattern B when the received signal is in an odd-order domain, andoutputs the output pattern A when the received signal is in aneven-order domain (as shown in FIG. 17).

Based on the above arrangement, in FIG. 16, for example, when thereceived baseband signal I+jQ shifts from the first domain to the seconddomain, the one-bit quantizer 403 outputs Q (a positive value) or−(I−Q)/√2 (a negative value), and outputs I (a positive value) or(I−Q)/√2 (a negative value) when the received signal shifts to thesecond domain. The absolute value of (I−Q)/√2 is close to zero, at aposition near the boundary between the first domain and the seconddomain, and the values of I and Q are substantially equal. Therefore,the change in the output from the converting selector 403 becomes small.

According to the present embodiment, even when the quadrant to which thereceived signal belongs changes, the change in the output from theconverting selector 403 becomes small, as the absolute value of (I−Q)/√2is close to zero at a position near the boundary between the quadrants,and also because the values of I and Q are substantially equal. As aresult, the phase detection value obtained by the delta sigma modulatorbecomes accurate. In the present embodiment, it is also possible to usethe sample holding circuit 3, like in the structure according to thethird embodiment.

In the first to the fifth embodiments, the phase detecting circuitincludes a first-order delta sigma modulator. In the sixth embodiment,the phase detecting circuit includes at least a second-order delta sigmamodulator. FIG. 20 shows a structure of the phase detecting circuitaccording to a sixth embodiment of the present invention. In FIG. 20, areference numeral 6 denotes an adder, and 7 denotes an integrator. InFIG. 20, the sections having the same structures as those in the firstto the third embodiments are attached with like reference numerals, andtheir explanation is omitted. In the present embodiment, the quadrantdeciding section 101, the rotation projector 4, the integrator 103, theadder 6, the integrator 7, the one-bit quantizer 5, the delay device105, and the adder 1 constitute the delta sigma modulator. The structureshown in FIG. 20 has the adder 6 and the integrator 7 added to thestructure (FIG. 4) according to the fourth embodiment, for convenienceof explanation. However, the structure of the present embodiment is notlimited to this structure. It is also possible to apply the adder 6 andthe integrator 7 to the structure (FIG. 1) according to the firstembodiment, or to the conventional structure (FIG. 30).

The operation of the phase detecting circuit according to the sixthembodiment is explained next. The sections attached with the samereference numerals as those in the phase detecting circuits according tothe first to the fifth embodiments carry out similar operationsrespectively.

The adder 6 adds the output from the rotation projector 4 and the outputfrom the integrator 103, and outputs the result of the addition to theintegrator 7. The one bit quantizer 5 quantizes the output (integrationresult) from the integrator 7, and outputs 0 or 1.

According to the present embodiment, the phase detecting circuitincludes at least the second-order delta sigma modulator. Based on thisstructure, the power spectrum of quantization noise becomes small at thelow-frequency side and becomes large at the high-frequency side.Therefore, by removing the high-frequency noise with the low-pass filter2, it becomes possible to substantially improve the signal-to-noiseratio, as compared with the phase detecting circuit that comprises thefirst-order delta sigma modulator like in the first to the fifthembodiments.

While the phase detecting circuit according to the present embodimentincludes at least the second-order delta sigma modulator for convenienceof explanation, the structure is not limited to this, and the phasedetecting circuit may be composed of at least the third-order deltasigma modulator. In the present embodiment, it is also possible to usethe sample holding circuit 3, like in the structure according to thethird embodiment.

In the sixth embodiment, the quadrant deciding section 101 quantizes thephase of the received signal in two bits. In the seventh embodiment, thequantization resolution is N (natural number) is explained. In thepresent embodiment, the phase detecting circuit includes at least thesecond-order delta sigma modulator.

FIG. 21 shows a structure of the phase detecting circuit according to aseventh embodiment of the present invention. The second-order deltasigma modulator shown in the present embodiment is based on, forexample, the structure of the second-order delta sigma modulator shownon page 37 of “Over-sampling A-D conversion technique”, Akira YUKAWA,Nikkei Business Publications, Inc. In FIG. 21, the sections having thesame structures as those in the first to the sixth embodiments areattached with like reference numerals, and their explanation is omitted.In the present embodiment, the phase quantizing section 401, theconverting selector 403, the integrator 103, the adder 6, the integrator7, the one-bit quantizer 5, the delay device 105, and the adder 1constitute the second-order delta sigma modulator. The structure shownin FIG. 21 has the adder 6 and the integrator 7 added to the structure(FIG. 13) according to the fifth embodiment, for convenience ofexplanation. However, the structure of the present embodiment is notlimited to this structure. It is also possible to apply the adder 6 andthe integrator 7 to the structure (FIG. 3) according to the secondembodiment, or to the conventional structure (FIG. 4).

The operation of the phase detecting circuit according to the seventhembodiment is explained next. The sections attached with the samereference numerals as those in the phase detecting circuits according tothe first to the sixth embodiments carry out similar operationsrespectively.

The adder 6 subtracts the output from the converting selector 403 fromthe output from the integrator 103, and adds the result of thesubtraction to the integrator 7. The one-bit quantizer 5 quantizes theoutput (integration result) from the integrator 7, and outputs 0 or 1.

FIG. 22 shows a structure of a phase detecting circuit different fromthe phase detecting circuit shown in FIG. 21. The second-order deltasigma modulator shown in this example is based on the structure of thesecond-order delta sigma modulator shown on page 43 of “Over-samplingA-D conversion technique”, Akira YUKAWA, Nikkei Business Publications,Inc. In FIG. 22, a reference numeral 8 denotes a delay device, and 9denotes an amplifier. In FIG. 22, the sections having the samestructures as those shown in FIG. 21 are attached with like referencenumerals, and their explanation is omitted. In FIG. 22, the phasequantizing section 401, the converting selector 403, the integrator 103,the delay device 8, the amplifier 9, the adder 6, the integrator 7, theone-bit quantizer 5, the delay device 105, and the adder 1 constitutethe second-order delta sigma modulator. The structure shown in FIG. 22has the adder 6, the integrator 7, the delay device 8, and the amplifier9 added to the structure (FIG. 13) according to the fifth embodiment,for convenience of explanation. However, the structure shown in FIG. 22is not limited to this structure. It is also possible to apply the adder6, the integrator 7, the delay device 8, and the amplifier 9 to thestructure (FIG. 3) according to the second embodiment, or to theconventional structure (FIG. 4).

The operation of the phase detecting circuit shown in FIG. 22 isexplained next. The sections attached with the same reference numeralsas those in the phase detecting circuits according to the first to thesixth embodiments carry out similar operations respectively.

The delay device 8 delays the output from the integrator 103 by onecycle, and outputs the delayed result to the adder 6. The integrator 9multiplies the output from the converting selector 403 by two, andoutputs the multiplied result to the adder 6. The adder 6 subtracts theoutput from the amplifier 9 from the output from the delay device 8, andoutputs the subtracted result to the integrator 7. The one-bit quantizer5 quantizes the output (integration result) from the integrator 7, andoutputs 0 or 1.

As explained above, when the delta sigma modulator is structured as thesecond-order delta sigma modulator, it is possible to shape noise suchthat the power spectrum density of quantization noise becomes small inthe low-frequency region of the signal band, and becomes large in thehigh-frequency region outside the signal band. Therefore, when thesubsequent low-pass filter 2 suppresses the high-frequency band, thetotal noise power becomes small as a result, and the signal-to-noiseratio improves.

In the present embodiment, the phase detecting circuit includes at leastthe second-order delta sigma modulator, as shown in FIG. 21 and FIG. 22.Based on this structure, the power spectrum density of quantizationnoise becomes small at the low-frequency side and becomes large at thehigh-frequency side. Therefore, by removing the high-frequency noisewith the low-pass filter 2, it becomes possible to substantially improvethe signal-to-noise ratio, as compared with the phase detecting circuitthat comprises the first-order delta sigma modulator like in the firstto the fifth embodiments.

While the phase detecting circuit according to the present embodimentincludes at least the second-order delta sigma modulator for convenienceof explanation, the structure is not limited to this, and the phasedetecting circuit may be composed of at least the third-order deltasigma modulator. In the present embodiment, it is also possible to usethe sample holding circuit 3, like in the structure according to thethird embodiment.

FIG. 23 shows a structure of a receiver comprising the phase detectingcircuit (the first to the seventh embodiments) according to an eighthembodiment of the present invention. In FIG. 23, the reference numerals301 and 302 denote the mixers, 303 denotes the local oscillator, 304denotes the quadrature divider, 305 and 306 denote the low-pass filters,307 and 308 denote the amplifiers, 11 denotes the phase detectingcircuit according to the first to the seventh embodiments, and 312denotes the demodulator. The phase detecting circuit 11 detects a phasefrom the in-phase component I and the quadrature component Q of thereceived baseband signal. The phase detecting circuit 11 can use any oneof the structures according to the first to the seventh embodiments. Thesections attached with the same reference numerals as those in theconventional phase detecting circuit carry out similar operationsrespectively.

As explained above, the receiver according to the present embodimentuses the phase detecting circuit that derives the quantized value of thephase from the tan θ that is the ratio of the in-phase component I tothe quadrature component Q of the received baseband signal, as explainedwith reference to the equation (11). Therefore, it is possible to detectthe phase regardless of the envelope amplitude of the received signal.As a result, the high-resolution A/D converter and the AGC that havebeen conventionally required are not necessary.

In the first to the fourth embodiments, the in-phase component and thequadrature component of the received baseband signal are input to thephase detecting circuit as single-end signals. The receiver shown inFIG. 23 has the structure of this example. The single-end input phasedetecting circuit 11 detects the phase from the in-phase component I andthe quadrature component Q of the single-end received baseband signal.Therefore, the phase quantizing section 401 and the converting selector402 have the following structures.

FIG. 24 shows the structure of the phase quantizing section (i.e., thequadrant deciding section) in the receiver shown in FIG. 23. When thequantization resolution of the phase quantizing section 401 is four (twobits), the phase quantizing section 401 includes comparators 210 and211, as shown in FIG. 24. FIG. 25 shows the structure of the convertingselector (i.e., the rotation projector) in the receiver shown in FIG.23. The converting selector 402 includes inverting amplifiers 212 and213, and a selector 214.

Each of the comparatos 210 and 211 compares the in-phase component Iwith the quadrature component Q of the received baseband signal, decidesthe sign, and outputs one-bit data. Each of the inverting amplifiers 212and 213 inverts the signs of the in-phase component I and the quadraturecomponent Q of the received baseband signal to set them to −I and−Qrespectively. The inverting amplifiers 212 and 213 input the signals I,Q, −I, and −Q to the selector 214. The selector 214 selects any one ofthe signals based on the signs of the signals output from the phasequantizing section 401 and the one-bit quantizer 5.

However, the receiver shown in FIG. 23 has the following problem whenthe received baseband signal is the single-end signal. When in-phasenoise or a DC offset is applied to the received baseband signal duringthe process from the output from the mixers 301 and 302 to the input tothe phase detecting circuit 11, it is difficult for the base bandlow-pass filters 305 and 306 and the amplifiers 307 and 308 to removethis noise or DC offset. When the in-phase noise and the DC offsetbecome large, it is not possible to accurately detect the phase.Further, when the gains of the inverting amplifiers 212 and 213 do notaccurately become −1 but become −a (where a≠1), the input to theselector 214 becomes I, Q, −aI, or −aQ, and it is not possible toaccurately detect the phase.

The present embodiment solves the above problems. FIG. 26 shows astructure of the receiver that has the phase detecting circuit accordingto the present invention. In FIG. 26, reference numerals 321 and 322denote mixers of differential outputs, 325 and 326 denote low-passfilters of differential inputs and outputs, 327 and 328 denoteamplifiers of differential inputs and outputs, and 12 denotes the phasedetecting circuit of differential inputs. In order to detect the phasefrom the in-phase component I and the quadrature component Q of thesingle-end received baseband signal, the phase detecting circuit 12 ofdifferential inputs has the phase quantizing section 401 and theconverting selector 402 in the following structures.

FIG. 27 shows the structure of the phase quantizing section (i.e., thequadrant deciding section) in the receiver according to the ninthembodiment. When the quantization resolution of the phase quantizingsection 401 is four (two bits), the phase quantizing section 401includes comparators 220 and 221, as shown in FIG. 27. FIG. 28 shows astructure of a converting selector (i.e., a rotation projector)according to the ninth embodiment. The converting selector 402 includesselectors 222, 223, and 226, and subtractors 224 and 225.

The comparator 220 decides the sign of the in-phase component I of thereceived baseband signal, by comparing a non-inversion signal I+ with aninversion signal I−, and outputs one-bit data. Similarly, the comparator221 decides the sign of the quadrature component Q of the receivedbaseband signal, by comparing a non-inversion signal Q+with an inversionsignal Q−, and outputs one-bit data. The selectors 222 and 223 selectwhich one of the non-inversion signal (I+, Q+) and the inversion signal(I−, Q−) is to be input to the minuend side, and which one of thesesignals is to be input to the subtrahend side, of the subtractors 224and 225 respectively, for the in-phase component I and the quadraturecomponent Q of the received baseband signal respectively, based on thesigns of the signals output from the phase quantizing section 401 andthe one-bit quantizer 5. Therefore, the subtractor 224 outputs any oneof I+−I−, and I−−I+, and the subtractor 225 outputs any one of Q+−Q−,and Q−−Q+. The selector 226 selectively outputs either the output fromthe subtractor 224 or the output from the subtractor 225, based on thesigns of the signals output from the phase quantizing section 401 andthe one-bit quantizer 5.

According to the present embodiment, the phase quantizing section 401and the converting selector 402 consist of differential structures.Therefore, even when the in-phase noise or the DC offset appears by thesame quantities in the non-inversion component and the inversioncomponent of the received baseband signal, it is possible to detect theaccurate phase by mutually canceling the noise or the offset. Thereoccurs no problem in the precision of the gain of the invertingamplifiers.

While the operations of the phase quantizing section 401 and theconverting selector 402 according to the present embodiment areexplained above, the structure is not limited to this. It is alsopossible to obtain similar effects based on the combination of the phasequantizing section 401 and the converting selector 403, and thecombination of the quadrant deciding section 101 and the rotationprojector 102, respectively.

FIG. 29 shows a structure of the demodulator 312 within the receivershown in FIG. 23. In FIG. 29, a reference numeral 13 denotes a timingrecovering section, 14 denotes a data deciding section, and 15 denotesan oscillator. In the present embodiment, FIG. 29 particularly shows thestructure of the phase detecting circuit 11 and the demodulator 312included in the digital frequency modulation (FSK) or the phasemodulation (PSK) receiver that comprises the phase detecting circuitaccording to the first to the seventh embodiments.

As explained above, the receiver usually detects the frequency or thephase of the received signal at intervals of ⅛ or {fraction (1/16)} ofthe symbol clock, and finds a suitable data decision timing from amongthese frequencies or phases. In the demodulator 312 shown in FIG. 29,the timing recovering section 13 receives the clock that is 16 times thesymbol clock oscillated by the oscillator 15, and the phase informationof the received signal output from the phase detecting circuit 11, andsearches the phase of the received signal for the data decision timingwith the resolution of {fraction (1/16)} of the symbol clock.

The timing recovering section 13 outputs a phase detection requesttiming signal to the phase detecting circuit 11. This phase detectionrequest timing signal is expressed in the values from 0 to 15, forexample. The timing recovering section 13 outputs the values from 0 to15 for each clock of 16 times the symbol clock, until when the datadecision timing is found after starting the signal reception. After thedata decision timing is found, the timing recovering section 13 outputsthe value of 0 at each one clock of the symbol clock, when the phase ofthe clock of 16 times the symbol clock is 0.

The phase detecting circuit 11 makes the adder 206, the comparing anddeciding section 204, the multipliers 202-1 to 202-k, and the dataconverters 205-1 to 205-k operate, at only the phase detection requesttiming instructed by the timing recovering section 13.

As explained above, the receiver according to the present embodimentmakes the low-pass filter 2 within the phase detecting circuit 11operate, at only the phase detection request timing instructed by thetiming recovering section 13. Therefore, it is possible to decreasepower consumption.

While the operation of the phase detecting circuit 11 shown in FIG. 23is explained as one example in the present embodiment, the phasedetecting circuit is not limited to this, and it is also possible toobtain similar effects from the phase detecting circuit 12 shown in FIG.26.

According to the present invention, the adding unit executes theaddition modulo the quantized value of the phase 2π. When the outputsfrom the shift registers to be executed include the phase data thatcross over the quantized value of 2π, the low-pass filter unit executesthe processing by converting the range 0 to 2π of the phase data to therange π to 37π, and thereafter returns the range of the phase data to 0to 2π. Based on this arrangement, it is possible to obtain the accurateresult of averaging the phase data. Therefore, there is an effect thatit is possible to realize accurate phase detection.

According to the next invention, the second quantizing unit quantizesthe output from the integrating unit by deciding the sign of this outputbased on the decided domain to which the received signal belongs.Further, the converting and selecting unit combines different outputpatterns for each domain, and outputs the result. Based on thisarrangement, there is an effect that the change in the output from theconverting and selecting unit becomes small, and the phase detectionvalue becomes more accurate.

According to the next invention, the first quantizing unit, theconverting and selecting unit, the integrating unit, the secondquantizing unit, the delay unit, and the adding unit constitute thedelta sigma modulator. Therefore, there is an effect that the low-passfilter unit can obtain the accurate result of averaging the phase data.

According to the next invention, the phase detecting circuit includes atleast the second-order delta sigma modulator. Based on this structure,the power spectrum of quantization noise becomes small at thelow-frequency side and becomes large at the high-frequency side.Therefore, there is an effect that by removing the high-frequency noisewith the low-pass filter unit, it becomes possible to substantiallyimprove the signal-to-noise ratio, as compared with the phase detectingcircuit that comprises the first-order delta sigma modulator.

According to the next invention, sample holding circuit is provided.Therefore, during the operation of the delta sigma modulator, the outputfrom the converting and selecting unit becomes constant. As a result,there is an effect that it is possible obtain the more accurate phasedetection value.

According to the next invention, the adding unit executes the additionmodulo the phase 2π. When the outputs from the shift registers to beexecuted include the phase data that cross over 2π, the low-pass filterunit executes the processing by converting the range 0 to 2π of thephase data to the range π to 3π, and thereafter returns the range of thephase data to 0 to 2π. Based on this arrangement, it is possible toobtain the accurate result of averaging the phase data. Therefore, thereis an effect that it is possible to realize accurate phase detection.

According to the next invention, the quadrant deciding unit, therotation projecting unit, the integrating unit, the quantizing unit, thedelay unit, and the adding unit constitute the delta sigma modulator.Therefore, there is an effect that the low-pass filter unit can obtainthe accurate result of averaging the phase data.

According to the next invention, the quantizing unit quantizes theoutput from the integrating unit by deciding the sign of this outputbased on the decided quadrant to which the received signal belongs. Inother words, the phase detecting circuit combines different outputpatterns for each quadrant, and outputs the result. Based on thisarrangement, there is an effect that the change in the output from therotation projecting unit becomes small, and the phase detection valuebecomes more accurate.

According to the next invention, the phase detecting circuit includes atleast the second-order delta sigma modulator. Based on this structure,the power spectrum of quantization noise becomes small at thelow-frequency side and becomes large at the high-frequency side.Therefore, there is an effect that by removing the high-frequency noisewith the low-pass filter unit, it becomes possible to substantiallyimprove the signal-to-noise ratio, as compared with the phase detectingcircuit that comprises the first-order delta sigma modulator

According to the next invention, during the operation of the delta sigmamodulator, the output from the rotation projecting unit becomesconstant. Therefore, there is an effect that it is possible obtain themore accurate phase detection value.

According to the next invention, the phase detecting circuit thatquantizes the ratio of the in-phase component I to the quadraturecomponent Q of the received baseband signal, is used. Therefore, thereis an effect that the high-resolution A/D converter and the AGC thathave been conventionally required are not necessary. Further, there isan effect that based on the use of the phase detecting circuit that canachieve accurate phase detection, it is possible to substantiallyimprove the distortion rate characteristic and the reception bit errorcharacteristic.

According to the next invention, the second quantizing unit quantizesthe output from the integrating unit by deciding the sign of this outputbased on the decided quadrant to which the received signal belongs. Inother words, the phase detecting circuit combines different outputpatterns for each quadrant, and outputs the result. Based on thisarrangement, there is an effect that the change in the output from therotation projecting unit becomes small, and the phase detection valuebecomes more accurate.

According to the next invention, the first quantizing unit and theconverting and selecting unit consist of differential structures.Therefore, there is an effect that even when the in-phase noise or theDC offset appears by the same quantities in the non-inversion componentand the inversion component of the received baseband signal, it ispossible to achieve accurate phase detection by mutually canceling thenoise or the offset.

According to the next invention, the phase detecting circuit thatquantizes the ratio of the in-phase component I to the quadraturecomponent Q of the received baseband signal, is used. Therefore, thereis an effect that the high-resolution A/D converter and the AGC thathave been conventionally required are not necessary. Further, there isan effect that based on the use of the phase detecting circuit that canachieve accurate phase detection, it is possible to substantiallyimprove the distortion rate characteristic and the reception bit errorcharacteristic.

According to the next invention, the quantizing unit quantizes theoutput from the integrating unit by deciding the sign of this outputbased on the decided quadrant to which the received signal belongs. Inother words, the phase detecting circuit combines different outputpatterns for each quadrant, and outputs the result. Based on thisarrangement, there is an effect that the change in the output from therotation projecting unit becomes small, and the phase detection valuebecomes more accurate.

According to the next invention, the quadrant deciding unit and therotation projecting unit consist of differential structures. Therefore,there is an effect that even when the in-phase noise or the DC offsetappears by the same quantities in the non-inversion component and theinversion component of the received baseband signal, it is possible toachieve accurate phase detection by mutually canceling the noise or theoffset.

According to the next invention, the phase detecting circuit includes atleast the second-order delta sigma modulator that has stages ofintegrators. Based on this structure, the power spectrum of quantizationnoise becomes small at the low-frequency side and becomes large at thehigh-frequency side. Therefore, there is an effect that by removing thehigh-frequency noise with the low-pass filter unit, it becomes possibleto substantially improve the signal-to-noise ratio, as compared with thephase detecting circuit that comprises the first-order delta sigmamodulator.

According to the next invention, the low-pass filter unit within thephase detecting circuit is operated at only the phase detection requesttiming instructed by the timing recovering unit. Therefore, there is aneffect that it is possible to substantially decrease power consumption.

According to the next invention, during the operation of the delta sigmamodulator, the output from the rotation projecting unit or theconverting and selecting unit becomes constant. Therefore, there is aneffect that it is possible to obtain the more accurate phase detectionvalue.

INDUSTRIAL APPLICABILITY

As explained above, the phase detecting circuit and the receiveraccording to the present invention are suitable for detecting the phaseof the FSK signal or the PSK signal in digital mobile communications.

1. A phase detecting circuit comprising: a first quantizing unit thatquantizes a phase of a received baseband signal; a converting andselecting unit that linearly converts the received signal based on apredetermined rule, and selectively outputs the signal after the linearconversion; an integrating unit that integrates the output from theconverting and selecting unit; a second quantizing unit that quantizesthe integration result by deciding the sign of the integration result; adelay unit that delays the output from the second quantizing unit by apredetermined first time, and outputs the delayed signal to theconverting and selecting unit; an adding unit that adds the output fromthe first quantizing unit and the output from the second quantizing unitmodulo the quantized value of the phase 2π; and a low-pass filter unitthat sequentially latches phase values after the addition with internalshift registers, converts the whole data within the shift registersbased on a predetermined rule when the phase values that cross over thequantized value of the phase 2π it exist in the whole data, does notcarry out the conversion when the phase values that cross over thequantized value of the phase 2π do not exist, averages the phase valuesin this state, and outputs the phase value after smoothing quantizationnoise.
 2. The phase detecting circuit according to claim 1, wherein thefirst quantizing unit, the converting and selecting unit, theintegrating unit, the second quantizing unit, the delay unit, and theadding unit constitute a delta sigma modulator.
 3. The phase detectingcircuit according to claim 2, further comprising a sample holdingcircuit unit that holds the received baseband signal at a constant levelduring a predetermined second time, at a pre-stage of the delta sigmamodulator.
 4. The phase detecting circuit according to claim 2, whereinthe delta sigma modulator comprises a plurality of stages ofintegrators.
 5. The phase detecting circuit according to claim 4,further comprising a sample holding circuit unit that holds the receivedbaseband signal at a constant level during a predetermined second time,at a pre-stage of the delta sigma modulator.
 6. A phase detectingcircuit comprising: a first quantizing unit that quantizes the phase ofa received baseband signal; a converting and selecting unit thatlinearly converts the received signal based on a predetermined rule, andselectively outputs the signal after the linear conversion; anintegrating unit that integrates the output from the converting andselecting unit; a second quantizing unit that quantizes the integrationresult by deciding the sign of the integration result based on theoutput from the first quantizing unit; a delay unit that delays theoutput from the second quantizing unit by a predetermined time, andoutputs the delayed signal to the converting and selecting unit; anadding unit that adds the output from the first quantizing unit and theoutput from the second quantizing unit modulo the quantized value of thephase 2π; and a low-pass filter unit that sequentially latches phasevalues after the addition with internal shift registers, converts thewhole data within the shift registers based on a predetermined rule whenthe phase values that cross over the quantized value of the phase 2πexist in the whole data, does not carry out the conversion when thephase values that cross over the quantized value of the phase 2π do notexist, averages the phase values in this state, and outputs the phasevalue after smoothing quantization noise.
 7. The phase detecting circuitaccording to claim 6, wherein the first quantizing unit, the convertingand selecting unit, the integrating unit, the second quantizing unit,the delay unit, and the adding unit constitute a delta sigma modulator.8. The phase detecting circuit according to claim 7, further comprisinga sample holding circuit unit that holds the received baseband signal ata constant level during a predetermined second time, at a pre-stage ofthe delta sigma modulator.
 9. The phase detecting circuit according toclaim 7, wherein the delta sigma modulator comprises stages ofintegrators.
 10. The phase detecting circuit according to claim 9,further comprising a sample holding circuit unit that holds the receivedbaseband signal at a constant level during a predetermined second time,at a pre-stage of the delta sigma modulator.
 11. A receiver comprising:a first quantizing unit that quantizes the phase of a received basebandsignal; a converting and selecting unit that linearly converts thereceived baseband signal based on a predetermined rule, and selectivelyoutputs the signal after the linear conversion; an integrating unit thatintegrates the output from the converting and selecting unit; a secondquantizing unit that quantizes the integration result by deciding thesign of the integration result; a delay unit that delays the output fromthe second quantizing unit by a predetermined first time, and outputsthe delayed signal to the converting and selecting unit; an adding unitthat adds the output from the first quantizing unit and the output fromthe second quantizing unit modulo the quantized value of the phase 2π; alow-pass filter unit that sequentially latches phase values after theaddition with internal shift registers, converts the whole data withinthe shift registers based on a predetermined rule when the phase valuesthat cross over the quantized value of the phase 2π exist in the wholedata, does not carry out the conversion when the phase values that crossover the quantized value of the phase 2π do not exist, averages thephase values in this state, and outputs the phase value after smoothingquantization noise; and a demodulator that demodulates the receptiondata based on the phase value, wherein the first quantizing unit, theconverting and selecting unit, the integrating unit, the secondquantizing unit, the delay unit, and the adding unit constitute a deltasigma modulator.
 12. The receiver according claim 11, whereindifferential inputs are applied to the first quantizing unit and theconverting and selecting unit.
 13. The receiver according claim 11,wherein the delta sigma modulator is in the M-order structure.
 14. Thereceiver according claim 11, wherein the demodulator comprises: a timingrecovering unit that receives a clock that is L times the symbol clockgenerated by an oscillator, and the phase value, searches the phasevalue for a data decision timing with the resolution of 1/L of thesymbol clock, and generates a phase detection request timing to operatethe low-pass filter unit; and a data deciding unit that decidesreception data based on the phase value and the data decision timing,wherein the low-pass filter unit operates at the phase detection requesttiming.
 15. The receiver according to claim 11, further comprising asample holding circuit unit that holds the amplified received basebandsignal at a constant level during a predetermined second time, at apre-stage of the delta sigma modulator.
 16. A receiver comprising: afirst quantizing unit that quantizes the phase of a received basebandsignal; a converting and selecting unit that linearly converts thereceived baseband signal based on a predetermined rule, and selectivelyoutputs the signal after the linear conversion; an integrating unit thatintegrates the output from the converting and selecting unit; a secondquantizing unit that quantizes the integration result by deciding thesign of the integration result based on the output from the firstquantizing unit; a delay unit that delays the output from the secondquantizing unit by a predetermined time, and outputs the delayed signalto the convening and selecting unit; an adding unit that adds the outputfrom the first quantizing unit and the output from the second quantizingunit modulo the quantized value of the phase 2π; a low-pass filter unitthat sequentially latches phase values after the addition with internalshift registers, converts the whole data within the shift registersbased on a predetermined rule when the phase values that cross over thequantized value of the phase 2π exist in the whole data, does not carryout the conversion when the phase values that cross over the quantizedvalue of the phase 2π do not exist, averages the phase values in thisstate, and outputs the phase value after smoothing quantization noise;and a demodulator that demodulates the reception data based on the phasevalue, wherein the first quantizing unit, the converting and selectingunit, the integrating unit, the second quantizing unit, the delay unit,and the adding unit constitute a delta sigma modulator.
 17. The receiveraccording claim 16, wherein differential inputs are applied to the firstquantizing unit and the converting and selecting unit.
 18. The receiveraccording claim 16, wherein the delta sigma modulator is in the M-orderstructure.
 19. The receiver according claim 16, wherein the demodulatorcomprises: a timing recovering unit that receives a clock that is Ltimes the symbol clock generated by an oscillator, and the phase value,searches the phase value for a data decision timing with the resolutionof 1/L of the symbol clock, and generates a phase detection requesttiming to operate the low-pass filter unit; and a data deciding unitthat decides reception data based on the phase value and the datadecision timing, wherein the low-pass filter unit operates at the phasedetection request timing.
 20. The receiver according to claim 16,further comprising a sample holding circuit unit that holds theamplified received baseband signal at a constant level during apredetermined second time, at a pre-stage of the delta sigma modulator.